Design and implementation of low-power SFQ circuits using LR-load biasing technique

We have considered LR-load biasing technique to reduce power consumption of SFQ circuits for the application of control circuits of superconducting qubits. In this technique a current bias circuit is composed of a large inductance Lb, a small resistance Rb and a small voltage source Vb. In order to demonstrate the validity of this technique, we have designed a low-power 8-bit SFQ clock generator (CG), which produces 28 SFQ pulses at 14.6 GHz. By employing the LR-load biasing technique, the power consumption of the CG was reduced to about 10% of its original version, which is biased using large bias resistance. We have implemented a test circuit of the CG using NEC 2.5 kA/cm2 Nb standard process and tested its operation and error rates. We have confirmed its correct operation with the dc bias margin of ±14.8% and obtained low enough error rates for the circuit application