Published October 2013 | Version v1
Journal article

Control and data acquisition ATCA/AXIe board designed for high system availability and reliability of nuclear fusion experiments

  • 1. Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade Técnica de Lisboa, 1049-001 Lisboa (Portugal)
  • 2. INESC-ID, Lisboa (Portugal)

Description

This paper describes the implementation and test of a control and data acquisition board designed to be integrated on systems demanding high availability and reliability, foreseen for future experiments like ITER or other long operation fusion devices. The Advanced Telecommunications Computing Architecture (ATCA) standard (PICMG 3.0 and 3.4) was selected for board implementation, which has support for the desired system robustness and performance. Some board features such as rear Input/Output (IO) signals connectivity (passive, copper tracks only), cable-less hot-swap maintenance, Intelligent Platform Management Controller (IPMC) and redundancy on timing signals, communications links and power supplies are significant board improvements, relatively to previous control and data acquisition boards, allowing the development of more reliable system architectures. Moreover, the developed board is also compatible with the emerging ATCA eXtensions for Instrumentation (AXIe) specifications, which provides additional timing and synchronization signals on the backplane. ATCA full-mesh, multi-gigabit, full-duplex, point-to-point communication links between Field Programmable Gate Arrays (FPGA), of peer boards inside the shelf, allow the implementation of distributed algorithms and development of Multi-Input Multi-Output (MIMO) systems. Up to 48 analog input channels, simultaneously digitized (2 MSPS @ 18-bits), are filtered/decimated by the board FPGA and sent to the ATCA/AXIe host through Peripheral Component Interconnect express (PCIe) using Direct Memory Access (DMA). In real-time, the host can update up to 48 analog output channels (1 MSPS @ 18-bits), per board, through PCIe. Further board characteristics comprise analog IO channels with galvanic isolation and an optional signal chopper mode, for offset compensation over time on digital integration of magnetic signals. Board time synchronization is attained by means of the Inter-Range Instrumentation Group (IRIG) time-code

Availability note (English)

Available from http://dx.doi.org/10.1016/j.fusengdes.2013.01.093

Additional details

Identifiers

DOI
10.1016/j.fusengdes.2013.01.093;
PII
S0920-3796(13)00103-8;

Publishing Information

Journal Title
Fusion Engineering and Design
Journal Volume
88
Journal Issue
6-8
Journal Page Range
p. 1332-1337
ISSN
0920-3796
CODEN
FEDEEE

Conference

Title
27. symposium on fusion technology
Acronym
SOFT-27
Dates
24-28 Sep 2012
Place
Liege (Belgium)

Optional Information

Copyright
Copyright (c) 2013 Elsevier Science B.V., Amsterdam, The Netherlands, All rights reserved.