Study on a robust insert-bump (ISB) bonding technique for a 3D package

The Cu pillar bump to Cu pillar bump bonding process, commonly used in bonding technology for the 3D stacking of TSV (through silicon via) formed chips, requires an additional process for the generation of bumps on the face and back-side of the chip, and it has a drawback in that it is structurally vulnerable to mechanical stresses, such as thermal stress. This study proposes an ISB (insert-bump) bonding process to overcome such drawbacks. Compared to the conventional Cu pillar bump to Cu pillar bump bonding process, the ISB bonding process has advantages in that it is simple and has high mechanical reliability of the package due to the mechanical interlocking. The stress distributions at the joints of the packages produced from Cu pillar bump to Cu pillar bump bonding and ISB processes were compared and analyzed through FEM analyses, and characteristics analyses of the fracture mode and joint characteristics; process variable optimization with respect to the bonding parameters was also conducted through experiments. The results of the analyses and experiments verified that the ISB bonding process yields a bonding strength of 917.6 mgf/bump, which is approximately twice as much as that of the conventional Cu pillar bump to Cu pillar bump bonding, and which yields a highly reliable mechanical structure. (paper)