Low-jitter on-chip clock for RSFQ circuit applications

The ultra-narrow linewidth of a long Josephson junction (LJJ) oscillator offers low timing jitter as a clock source. In this paper, we will discuss the improvement of an LJJ clock by using an annular geometry. We demonstrate the integration of an annular LJJ with a clock decimator which consists of a serial chain of toggle-flip-flops (TFFs). Each TFF divides its input frequency by a factor of 2. We have also developed a clock frequency selector. The clock selector circuit can choose either the master clock fm or one of its sub-harmonics (fm/2m, m=1 to n), based on the select inputs. The generation of a set of clocks will enable us to integrate the on-chip LJJ clock with a flash analogue-to-digital converter. (author)