Design rules for superconducting analog-digital transducers

This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducting ADC's is proved.