Utilizing a multiprocessor architecture - The performance of MIDAS
- 1. Lawrence Berkeley Lab., Univ. of California, Berkeley, CA 94720
Description
The MIDAS architecture organizes multiple CPUs into clusters called distributed subsystems. Each subsystem consists of an array of processors controlled by a supervisory CPU. The multiprocessor array is composed of commercial CPUs (with floating point hardware) and specialized processing elements. Interprocessor communication within the array may occur either through switched memory modules or common shared memory. The architecture permits multiple processors to be focused on single problems. A distributed subsystem has been constructed and tested. It currently consists of a supervisor CPU; 16 blocks of independently switchable memory; 9 general purpose, VAX-class CPUs; and 2 specialized pipelined processors to handle I/O. Results on a variety of problems indicate that the subsystem performs 8 to 15 times faster than a standard computer with an identical CPU. The difference in performance represents the effect of differing CPU and I/O requirements
Additional details
Publishing Information
- Journal Title
- IEEE Trans. Nucl. Sci.
- Journal Volume
- NS-30
- Journal Issue
- 5
- Series
- IEEE Trans. Nucl. Sci.
- Journal Page Range
- 3827-3832
- ISSN
- 0018-9499
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 15062336
- Subject category
- S99: GENERAL AND MISCELLANEOUS;
- Descriptors DEI
- DEC COMPUTERS; MEMORY DEVICES; MIDAS COMPUTER; NUCLEAR INSTRUMENT MODULES; PERFORMANCE; SPECIFICATIONS
- Descriptors DEC
- COMPUTERS