Development of a test environment for the characterization of the current digitizer chip DCD2 and the DEPFET pixel system for the Belle II experiment at superKEKB

The future super flavor factory SuperKEKB with its detector system Belle II offers precision physics measurements to verify the Standard Model or probe undiscovered phenomena beyond its limits. A two layer vertex pixel detector is built based on the DEPFET technology. The Depleted Field Effect Transistor (DEPFET) pixel structure is an advanced type of silicon semiconductor detector, which provides simultaneously position sensitive detector capabilities and internal amplification. Fast and low noise readout of large area DEPFET sensors with row rates of 10 MHz is required. A new readout chip, the Drain Current Digitizer (DCD2), is available, which allows parallel readout of multiple channels with on-chip signal digitization. For the full characterization of this ASIC a FPGA based readout system has been designed, which also allows the operation of a prototype system including a DEPFET sensor. In this thesis, detailed measurements of the standalone performance of the DCD2 and the full system are presented; a limit on the possible readout speed of a large DEPFET sensor is established, and a switch from the slower double sampling readout scheme to a faster single sampling scheme is motivated. (orig.)