FPGA based data reduction algorithm for the Belle-II DEPFET detector

The readout system of the pixel detector (PXD) at the future Belle-II experiment will have to cope with an estimated input data rate of ≤21.6 GB/s. The hardware platform of the readout system is going to be ATCA-based Compute Node (CN) with Xilinx Virtex-5 FX70T FPGAs. The large data rate must be reduced by a factor ∝10 before being send to the event builder. The reduction is done by a region-of-interest (ROI) algorithm based upon e.g. track finding on the high level trigger (HLT). The free/occupied buffer management, ROI selection, and data unpacking algorithms, programmed in VHDL for the FPGAs, will be explained in detail. Performance results for 100/200 MHz clocks and 32/64 bit bus width are presented.