A proposed SEU tolerant dynamic random access memory (DRAM) cell

A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated breakdown diode is proposed. This design offers considerable resistance to single event cell errors. The informational charge packet is shielded from the single event by placing the vulnerable node in a self-compensating state while the cell is in standby mode. The proposed cell is comparable in size to a conventional DRAM cell, and computer simulations show an improvement in critical charge of two orders of magnitude over conventional 1-T DRAM cells