Asymmetrical increase of memory window in MFIS devices after avalanche electron injection

We investigated the effects of charge trapping on the asymmetrical increase in the memory window of metal-ferroelectric-insulator-semiconductor (MFIS) devices. We suggest that defect centers located at the ferroelectric-insulator interface play important roles in generating the asymmetrical increase in the memory window: Electron trapping at/near the SBN (or SBT)-Y2O3 interface via avalanche electron injection from the Si substrate results in the preferential domain switching, causing the asymmetrical increase in the memory window