A low jitter, low spur multiphase phase-locked loop for an IR-UWB receiver

A low jitter, low spur multiphase phase-locked loop (PLL) for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The PLL is based on a ring oscillator in order to simultaneously meet the jitter requirement, low power consumption and multiphase clock output. In this design, a noise and matching improved voltage-controlled oscillator (VCO) is devised to enhance the timing accuracy and phase noise performance of multiphase clocks. By good matching achieved in the charge pump and careful choice of the loop filter bandwidth, the reference spur is suppressed. A phase noise of -118.42 dBc/Hz at a frequency offset of 1 MHz, RMS jitter of 1.53 ps and reference spur of -66.81 dBc are achieved at a carrier frequency of 264 MHz in measurement. The chip was manufactured in 0.13 μm CMOS technology and consumes 4.23 mW from a 1.2 V supply while occupying 0.14 mm2 area. (semiconductor integrated circuits)