Design of fast Josephson arithmetic circuits

This paper reports on a Josephson 2-bit full adder and a 4-bit parallel multiplier designed using an advanced design with speed optimization of function direct coupled logic (ADCL). wide margins EXOR, Majority 2/3 and Delay gates implemented with picosecond junctions (RNC = 2ps) are presented and their performances are analyzed. The adder consists of 10 gates with 90 Josephson junctions and dissipates 30μW. The propagation time along the critical path is 10ps/bit near threshold bias. It rises only at 20ps/bit in the adder at 80% of the maximum bias. The multiplier consists of 60 gates and dissipates 180μW. The propagation times along the critical path near threshold bias and at 80% of maximum bias are respectively 60 ps/bit and 100 ps/bit