An adaptive high-throughput edge detection filtering system using dynamic partial reconfiguration

This paper proposes an architecture consisting of various edge detection filters implemented on modern FPGA platforms exploiting a feature of dynamic partial reconfiguration (DPR). The developed system targets small-scale systems, and its use in the educational setting can be of great interest. Two-dimensional convolution is the most common operation in digital video/image processing, and its implementation is highly demanding in terms of computational intensity, high throughput and hardware resources. In the case of a variety of filtering techniques used for edge detection, the hardware resources become a constraint, in particular when using convolution kernels with varying parameters and sizes. DPR introduces significant functional density and increased flexibility by providing logic switching within a constrained hardware area. Furthermore, parallel and pipelined hardware solutions for filter implementation overcome computational performance of software solutions and increase effectiveness compared to static hardware solution. The advantages of accommodating a number of various algorithms within the same datapath at low cost and considerable time are exploited in the proposed work. The effectiveness of the DPR feature for edge detection application is tested on the filter scenarios varying in sizes, complexity and intensity of computation, where the resource utilization and timing are evaluated. Experimental results are proposed through comparisons between different configurations (with DPR and without DPR) and detailed performance analysis.