Digital coincidence detection: A scanning VLSI implementation

The authors have implemented a modular digital coincidence detection circuit in VLSI, which drastically reduces the size, and increases the performance of the coincidence detection logic required in a PET scanner. Important acquisition features contained within this integrated solution include: (1) prompt and delayed processing channels for each event-pair, with programmable coincidence time windows; (2) event time difference mode, which allows for a fast and accurate system timing calibration algorithm; (3) programmable axial event acceptance, which provides acquisition flexibility from conventional 2D through fully-3D sinogram sets and (4) programmable transaxial field of view, which provides an ''electronic'' collimator to ignore event-pairs outside of the desired field of view. The modularity of the design allows it to be used on various system geometries