Published December 7, 2011 | Version v1
Journal article

Designer hydride routes to 'Si–Ge'/(Gd,Er)2O3/Si(1 1 1) semiconductor-on-insulator heterostructures

  • 1. Department of Chemistry and Biochemistry, and Department of Physics, Arizona State University, Tempe, AZ 85287 (United States)

Description

We demonstrate Si–Ge integration on engineered M2O3/Si(1 1 1) (M = Gd,Er) dielectric buffer layers using non-traditional chemical precursors that provide new levels of functionality within the deposition process. Stoichiometric Si0.50Ge0.50 alloys and pure Si heterostructures are grown epitaxially via ultra-low-temperature chemical vapor deposition using SiH3GeH3 and Si3H8/Si4H10, respectively. In the case of Si on Gd2O3, an optimal growth processing window in the range of 500–600 °C was found to yield planar layers with monocrystalline structures via a proposed coincidence lattice matching mechanism (2aSi–aGd2O3), while for the SiGe system (2% lattice mismatch) comparable quality films with fully relaxed strain states are deposited at a lower temperature range of 420–450 °C. Extension of this growth process to Si on Er2O3 yields remarkably high-quality layers in spite of the even larger ∼3% lattice mismatch. In all cases, the Si–Ge overlayers are found to primarily adopt an A–B–A epitaxial alignment with respect to the M2O3 buffered Si(1 1 1). A comparative study of the Si growth using Si3H8 and Si4H10 indicates that both compounds provide an efficient and straightforward process for semiconductor growth on Gd2O3/Si(1 1 1), which appears to be more viable than conventional approaches from the point of view of scalability and volume

Availability note (English)

Available from http://dx.doi.org/10.1088/0268-1242/26/12/125005

Additional details

Identifiers

DOI
10.1088/0268-1242/26/12/125005;
PII
S0268-1242(11)00715-2;

Publishing Information

Journal Title
Semiconductor Science and Technology
Journal Volume
26
Journal Issue
12
Journal Page Range
[9 p.]
ISSN
0268-1242
CODEN
SSTEET