A massively parallel processor for level 2 muon triggers at D0

The level 2 muon trigger for the upgraded D0 detector is based on finding either a track segment directly outside the calorimeter or a full track that includes hits on either side of the magnetized iron toroid. The architecture for level 2 includes the use of a preprocessor which will be used to find the segments. Queueing simulation of the level 2 architecture shows a strong dependence between deadtime and large events in the preprocessors when a serial computation is performed. By using a parallel preprocessor architecture where each individual processor focuses on a narrow path through the detector, the effect of large events or slow calculations on deadtime is eliminated. The CNAPS commercial parallel processor board is considered for the muon preprocessor. (orig.)