Published February 1985
| Version v1
Journal article
The design of a semi-custom intergrated circuit for the SLAC SLC timing control system
Description
A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given
Additional details
Publishing Information
- Journal Title
- IEEE Trans. Nucl. Sci.
- Journal Volume
- NS-32
- Journal Issue
- 1
- Series
- IEEE Trans. Nucl. Sci.
- Journal Page Range
- 87-88
- ISSN
- 0018-9499
- CODEN
- IETNA
Conference
- Title
- Nuclear science symposium.
- Dates
- 31 Oct - 2 Nov 1984.
- Place
- Orlando, FL (USA).
INIS
- Country of Publication
- United States
- Country of Input or Organization
- United States
- INIS RN
- 17051084
- Subject category
- S43: PARTICLE ACCELERATORS;
- Resource subtype / Literary indicator
- Conference
- Descriptors DEI
- INTEGRATED CIRCUITS; PERFORMANCE; SPECIFICATIONS; STANFORD LINEAR COLLIDER; TIMING CIRCUITS
- Descriptors DEC
- ACCELERATORS; ELECTRONIC CIRCUITS; LINEAR ACCELERATORS
Optional Information
- Secondary number(s)
- CONF-841007--.