Development of high level trigger for PANDA EMC using an FPGA-based compute node

The PANDA experiment at FAIR has a rich physics program. The EMC detector provides almost 4π coverage, good granularity and good energy resolution. Its data acquisition(DAQ) system features a novel self-trigger data pushed architecture. Data from EMC readout electronics are processed on the fly to reconstruct electromagnetic showers. The extracted features are combined with information from other detectors in order to discriminate photons from electrons and hadrons. The EMC detector, readout electronics and offline reconstruction algorithms are studied and an adaptive EMC DAQ scheme is proposed employing an FPGA based Compute Node(CN). The CN provides flexible connections with high bandwidth between processing modules, up to 10 GByte DDR2 memory per board for data buffering and five high-end FPGAs for sophisticated algorithm applications. The algorithm partition strategy is designed based on the readout electronics layout and the CN's processing architecture. The functional verification and performance evaluation methods for the algorithms are also covered.