Tests of final hardware revision of the Belle II PXD data reduction system

The Belle II physics data taking is scheduled in October 2018, with a planned factor ≤ 40 higher luminosity as its predecessor, the Belle experiment. For the pixel detector (PXD) DEPleted Field Effect Transistors (DEPFET) are used, with ∝ 8 x 10⁶ pixels in total. As increased luminosity implies increased background, online filtering of incomning raw data of ∝ 20 GB/s is a crucial part of the PXD readout chain. The hardware platform is based upon ATCA (Advanced Telecommunications Architecture), Xilinx Virtex-5 FX70T FPGAs and high speed optical link technology (6.5 Gbps), and called ONline SElection Nodes (ONSEN). The reduction is based on calculated Regions-Of-Interest (ROIs), calculated by a high level trigger running on a PC farm. The full ONSEN system consists of 9 ATCA carrier boards with 33 daughter cards. Tests procedures for final hardware are presented.