New electronics for the Cherenkov Telescope Array (NECTAr)

The international CTA consortium has recently entered into its preparatory phase towards the construction of the next-generation Cherenkov Telescope Array CTA. This experiment will be a successor, and based on the return of experience from the three major current-generation arrays H.E.S.S., MAGIC and VERITAS, and aims to significantly improve upon the sensitivity as well as the energy range of its highly successful predecessors. Construction is planned to begin by 2013, and when finished, CTA will be able to explore the highest-energy gamma ray sky in unprecedented detail. To achieve this increase in sensitivity and energy range, CTA will employ the order of 100 telescopes of three different sizes on two sites, with around 1000–4000 channels per camera, depending on the telescope size. To equip and reliably operate the order of 100000 channels of photodetectors (compared to 6000 of the H.E.S.S. array), a new kind of flexible and powerful yet inexpensive front-end hardware will be required. One possible solution is pursued by the NECTAr (New Electronics for the Cherenkov Telescope Array) project. Its main feature is the integration of as much as possible of the front-end electronics (amplifiers, fast analogue samplers, memory and ADCs) into a single ASIC, which will allow very fast readout performances while significantly reducing the cost and the power consumption per channel. Also included is a low-cost FPGA for digital treatment and online data processing, as well as an Ethernet connection. Other priorities of NECTAr are the modularity of the system, a high degree of flexibility in the trigger system as well as the possibility of flexible readout modes to optimise the signal-to-noise ratio while at the same time allowing a significant reduction of data rates, both of which could improve the sensitivity of CTA compared to current detection systems. This paper gives an overview over the development work for the Nectar system, with particular focus on its main component, the NECTAr ASIC.