Published May 4, 2015 | Version v1
Journal article

Design, fabrication, and performance analysis of GaN vertical electron transistors with a buried p/n junction

  • 1. Electrical and Computer Engineering Department, University of California Santa Barbara, Santa Barbara, California 93106 (United States)
  • 2. Materials Department, University of California Santa Barbara, Santa Barbara, California 93106 (United States)
  • 3. School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, Arizona 85287 (United States)

Description

The Current Aperture Vertical Electron Transistor (CAVET) combines the high conductivity of the two dimensional electron gas channel at the AlGaN/GaN heterojunction with better field distribution offered by a vertical design. In this work, CAVETs with buried, conductive p-GaN layers as the current blocking layer are reported. The p-GaN layer was regrown by metalorganic chemical vapor deposition and the subsequent channel regrowth was done by ammonia molecular beam epitaxy to maintain the p-GaN conductivity. Transistors with high ON current (10.9 kA/cm2) and low ON-resistance (0.4 mΩ cm2) are demonstrated. Non-planar selective area regrowth is identified as the limiting factor to transistor breakdown, using planar and non-planar n/p/n structures. Planar n/p/n structures recorded an estimated electric field of 3.1 MV/cm, while non-planar structures showed a much lower breakdown voltage. Lowering the p-GaN regrowth temperature improved breakdown in the non-planar n/p/n structure. Combining high breakdown voltage with high current will enable GaN vertical transistors with high power densities

Additional details

Identifiers

Publishing Information

Journal Title
Applied Physics Letters
Journal Volume
106
Journal Issue
18
Journal Page Range
p. 183502-183502.5
ISSN
0003-6951
CODEN
APPLAB

Optional Information

Notes
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