Analysis of 1.2 kV SiC buried-grid VJFETs

1.2 kV buried-grid vertical 4H-SiC JFET structures with normally-on (N-on) and normally-off (N-off) designs were investigated by simulation. The static and dynamic characteristics of the devices were determined over a wide range of current, voltage and gate drive conditions in the temperature range -50 0C to 250 0C. In this paper, the properties of the N-on designs with threshold voltages (Vth) -50 and -10 V are compared with the properties of the N-off design (Vth=0). For constant Vth, on-resistance decreases and output current increases with increasing channel doping and decreasing channel width. Simulations show that an on-resistance lower than 2 mΩ cm2 at 250 0C can be obtained provided the channel width is smaller than 1.5 and 0.5 μm for N-on JFETs with Vth=-50 V and Vth=-10 V, respectively, and lower than 3 mΩ cm2 provided the channel width is smaller than 0.3 μm for the N-off JFET. At the same time, Eon decreases and Eoff increases with increased channel doping concentration and reduced channel width. It is shown that Eon decreases with increasing channel doping concentration due to the reduced channel resistance for the faster turn-on process. Eoff increases with increasing channel doping concentration due to the increase in gate-drain capacitance, CGD.