Design of prototype Front-End Electronics for the Gamma-Gamma collider

The Gamma-Gamma collider is a scientific facility proposed in China to observe two unique interactions at the center-of-mass energy of 1–2 MeV, namely $\gamma \gamma$ scattering and electron-positron pairs. In the experiment, two $\gamma$ beams generated by the Compton back-scattering of high-energy electron beams ($\sim 200$ MeV) and high-intensity laser beams will collide at the interaction point, and the products will be collected by CsI(Na) crystals and plastic scintillators, and then converted into electric signals by silicon photomultiplier (SiPM) detectors. In this paper, a prototype Front-End Electronics (FEE) is implemented to verify the design requirements concerning the noise level (no more than 3 mV), high sampling rate (1 GS/s) and low power consumption. The prototype FEE comprised 8 differential drivers, 2 low-power switch capacitor array (SCA) DRS4 chips, and an 8-channel Analog-to-Digital Converter (ADC). The input signals were first stored in DRS4 chips for time stretching, then digitized by the ADC, and finally sent to back-end electronics via an optical link. The noise (RMS) of each readout channel on the prototype FEE was less than 3 mV after offset correction, and the ENOB of the channels was better than 6.7 bit when the frequency of input sine waves was less than 70 MHz and the sampling rate of the DRS4 was 1 GS/s. Therefore, the performance of the prototype FEE meets the requirements of the Gamma-Gamma collider.