Testing and characterization of a new pixel front-end IC in 3D integration technology for upgraded LHC

ATLAS is one of the four main particle detectors located on the LHC ring at CERN. The upcoming upgrades (Insertable B-Layer ∝2014 and High Luminosity LHC ∝2020) assume luminosity ramp-up up to 1035 cm-2s-1 and as a result higher particle multiplicity. This in turn makes complicated the usage of the current pixel detector Front End (FE) FE-I3 since its architecture is not tuned for the higher hit rates and becomes inefficient. A new FE with an architecture adapted to higher occupancies is therefore needed. In parallel to the new FE-I4 designed in 130 nm CMOS technology, a similar IC is being developed in a so-called 3D technology. This technology gives the possibility to split the IC into several active parts (tiers) and combine them using Through Silicon Via and bonding techniques into one package. Such kind of integration leads to a smaller pixel size and allows choosing for each tier a suitable technology. It is widely believed that 3D integration is the future for chip design in general and particularly for HEP applications. As 3D integration is new for the HEP community, special attention should be brought to the prototype IC testing and characterization. In this talk, a description of the new FETC4 architecture as well as first test results is presented.