Electronic properties of dislocations introduced mechanically at room temperature on a single crystal silicon surface

This paper focuses on the effects of temperature and environment on the electronic properties of dislocations in n-type single crystal silicon near the surface. Deep level transient spectroscopy (DLTS) analyses were carried out with Schottky electrodes and p+-n junctions. The trap level, originally found at EC-0.50 eV (as commonly reported), shifted to a shallower level at EC-0.23 eV after a heat treatment at 350 K in an inert environment. The same heat treatment in lab air, however, did not cause any shift. The trap level shifted by the heat treatment in an inert environment was found to revert back to the original level when the specimens were exposed to lab air again. Therefore, the intrinsic trap level is expected to occur at EC-0.23 eV and shift sensitively with gas adsorption in air.