Notes on the fast bus system

The Advanced Systems Design Group was formed to specify and design a system for a new standard for data acquisition in high-energy physics. The design work is reasonably far along; an abbreviated progress report is presented here. In any system there will be modules that gather and process data from the experiment's detectors and perhaps from other sources such as the accelerator control system or monitoring system. In order to have a general system these modules must be able to communicate with each other and perhaps with a host computer or a group of controlling computers. A very general communications system is the bus system, used in computers, in which all devices are connected in parallel to a group of lines, typically 50 to 100. By means of a protocol of communication on some of these lines, a device that wants to control the bus makes its wishes known. If the device is the highest priority one currently asking for the bus, it gains bus mastership and then signals another device that it wants to communicate with by means of a set of address lines. This system works very well in a computer that includes a processor, memory, and peripheral devices; its disadvantages are that only one device can be bus master at a time and only one communication can take place at a time. The proposed solution to this problem is to segment the bus so that each segment can operate independently without interfering with another one. This allows a large amount of parallel operation. It is necessary for one segment to communicate with other ones at some point in the process, and this is achieved by a device called the segment interconnect (SI).Much of the character of the system will be determined by the details of the SI. One possibility is a device that passes information only when the address falls within a band of values (or perhaps several bands); details of its specification are being worked on now