Published November 1, 2001 | Version v1
Report

A Dual Digital Signal Processor VME Board for Instrumentation and Control Applications

Description

A Dual Digital Signal Processing VME Board is being developed for the CEBAF Beam Current Monitor system at Jefferson Lab. It is a versatile general-purpose digital signal processing board using an open architecture, which allows for adaptation to various applications. The base design uses two independent Texas Instrument (TI) TMS320C6711, which are 900 MFLOPS floating-point digital signal processors (DSP). Applications that require a fixed point DSP can be implemented by replacing the baseline DSP with the pin-for-pin compatible TMS320C6211. Both parallel and serial protocols have been implemented for communicating with off board devices. The initial implementation makes use of TI Multi-channel Serial protocol and VME bus protocol. Other communication protocols can be implemented by reprogramming the FPGA. Each DSP is equipped with FLASH PROM and SDRAM for program and data storage. Additionally, each DSP has 16 bits of digital I/O, two digital analog converters, and two analog to digital converters. Dual 160 pins mezzanine connectors provide expansion capability without design modifications. The mezzanine interface conforms to the TI Expansion Daughter Card Interface standard. The design can be manufactured with a reduced chip set without redesigning the printed circuit board. For example, it can be implemented as a single-channel DSP with no analog I/O. The board supports JTAG 1149 boundary scan to facilitate testing, debugging, and programming. It is fully programmable using software development tools such as TI Code Composer Studio and a JTAG emulator such as Spectrum Digital DS510PP-PLUS. Using these tools allows one program the flash memory and FPGA through the JTAG ports, thus eliminating the need for a separate ROM/FPGA programmer. This work supported by U.S. DOE Contract No. DE-AC05-84ER40150

Availability note (English)

Available from PURL: https://www.osti.gov/servlets/purl/788815-8yImfy/native/

Additional details

Publishing Information

Imprint Pagination
189 Kilobytes
Report number
JLAB-ACE--01-14

Conference

Title
ICALEPCS 2001
Dates
27-30 Nov 2001
Place
San Jose, CA (United States)

INIS

Country of Publication
United States
Country of Input or Organization
United States
INIS RN
33002486
Subject category
S43: PARTICLE ACCELERATORS; S99: GENERAL AND MISCELLANEOUS;
Resource subtype / Literary indicator
Conference, Non-conventional Literature
Descriptors DEI
ANALOG-TO-DIGITAL CONVERTERS; BEAM CURRENTS; BEAM MONITORS; CEBAF ACCELERATOR; COMPUTERIZED CONTROL SYSTEMS; DESIGN; MODIFICATIONS; PRINTED CIRCUITS; SIGNAL CONDITIONING
Descriptors DEC
ACCELERATORS; CONTROL SYSTEMS; CURRENTS; ELECTRONIC CIRCUITS; ELECTRONIC EQUIPMENT; EQUIPMENT; LINEAR ACCELERATORS; MEASURING INSTRUMENTS; MONITORS; ON-LINE CONTROL SYSTEMS; ON-LINE SYSTEMS

Optional Information

Contract/Grant/Project number
AC05-84ER40150
Funding organization
USDOE Office of Energy Research (ER) (United States)
Secondary number(s)
DOE/ER--40150-1949