Published November 1, 1999
| Version v1
Journal article
A high speed Sorting Processor ASIC for the RPC Trigger system of the CMS experiment
Creators
Description
The design of a high speed Sorting Processor ASIC is presented. It was designed in BiCMOS 0.8 μm technology and its aim is to reorder and provide the four highest words among eight input words, in decreasing order. This chip is the main component of the sorting tree of the Trigger Muon System of the CMS experiment
Additional details
Identifiers
- PII
- S0168900299004702;
Publishing Information
- Journal Title
- Nuclear Instruments and Methods in Physics Research. Section A, Accelerators, Spectrometers, Detectors and Associated Equipment
- Journal Volume
- 436
- Journal Issue
- 3
- Journal Page Range
- p. 394-400
- ISSN
- 0168-9002
- CODEN
- NIMAER
INIS
- Country of Publication
- Netherlands
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 34038092
- Subject category
- S46: INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND TECHNOLOGY;
- Descriptors DEI
- DIGITAL FILTERS; FREQUENCY ANALYSIS; MICROPROCESSORS; MUON DETECTION; TRIGGER CIRCUITS
- Descriptors DEC
- CHARGED PARTICLE DETECTION; DETECTION; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; PULSE CIRCUITS; RADIATION DETECTION
Optional Information
- Copyright
- Copyright (c) 1999 Elsevier Science B.V., Amsterdam, The Netherlands, All rights reserved.