Stabilization of accelerating field using FPGA for J-PARC linac

The FPGA based digital RF feedback (FB) system installed in a compact PCI (cPCI) is applied to the J-PARC linac in order to realize the accelerating field stability of ±1% in amplitude and ±1 degree in phase. The FPGA board with software developed using Xilinx ISE performs the real time feedback calculation of the accelerating field. A DSP board is used for digital signal processing and monitoring, cavity tuner controlling, and communication between FPGA and CPU. The FPGA feedback control system will be explained in detail in this paper. The feedback and cavity tuner control tests with the newly improved software have been performed by using DTL2 cavities and waveguides in June and July 2006, and the required stability of the accelerating filed has been successfully achieved. (author)