System of ispFlash configuration

The aim of this module is to allow the use of FPGA components instead of EPLD components which for an equivalent or even inferior capacity are more expensive. For instance, the idea is to replace CPLD components having 512 macro-cells by one FPGA spartan II of Xilinx. However, due to the configuration's volatility, one configuration means is needed to put under voltage. A solution appears to be the using of a high capacity Flash memory coupled to a CPLD of small size to comply with the FPGA configuration protocol; also, one has to provide an in situ configuration means for this memory. Obviously, a product having an equivalent functionality already exists, since Xilinx and ALTERA supply PROMs of serial configuration. Unfortunately, they are expensive and a dealer is implied while the FLASH, the small CPLD and the FPGA spartan II are currently available. In conclusion, by using this assembly, which requires a small supplementary surface and a delay of upmost 240 ms (for the largest FPGA 1 Mbit), one obtains a solution cheaper and more performing than an EPLD of high capacity