Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time. The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation. A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D (source/drain) region. It is found that an optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure. Further, the proposed structure had improved off current, subthreshold slope and drain induced barrier lowering (DIBL) characteristics. It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance. (semiconductor devices)