Published October 28, 1964
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Study and realisation of the arithmetic unit of an information processing machine
Description
After having defined the arithmetic unit of an information processing machine, and its role, and described the main characteristics of two types of machine (fixed or varying word length), the author of this research thesis reports the study of a decimal adder, describes the operation of a synchronous arithmetic unit for a varying word length machine, reports the technological study of the arithmetic unit (electronic components and circuits, printed circuits), and finally presents multiplication and division subroutines
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47078141.pdf
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Additional details
Additional titles
- Original title (French)
- Etude et realisation de l'unite arithmetique d'une machine de traitement de l'information
Identifiers
Publishing Information
- Imprint Pagination
- 179 p.
- Report number
- FRCEA-TH--7336
INIS
- Country of Publication
- France
- Country of Input or Organization
- France
- INIS RN
- 47078141
- Subject category
- S97: MATHEMATICAL METHODS AND COMPUTING;
- Resource subtype / Literary indicator
- Thesis
- Descriptors DEI
- COMPUTERS; DATA PROCESSING; DIGITAL COMPUTERS; DIGITAL SYSTEMS; ELECTRONIC CIRCUITS; ELECTRONIC EQUIPMENT; INFORMATION; INFORMATION THEORY; MATHEMATICAL LOGIC; PROGRAMMING; SIGNAL CONDITIONING
- Descriptors DEC
- COMPUTERS; EQUIPMENT; PROCESSING
Optional Information
- Notes
- 11 refs.; Available from the INIS Liaison Officer for France, see the 'INIS contacts' section of the INIS website for current contact and E-mail addresses: http://www.iaea.org/inis/Contacts/