Analysis of trap generation during programming/erasing cycling in silicon nanocrystal memory devices

Trap generation of a nonvolatile silicon-nanocrystal memory during Fowler–Nordheim programming/erasing (P/E) cycling is analyzed using the combination of capacitance–voltage and current–voltage measurements. With increasing the number of P/E cycles, the flatband voltage decreases due to hole trapping in the accumulation; the threshold voltage increases due to electron trapping in the inversion. The generation of hole and electron trapping is explained by an anode hole injection mechanism and a cathode injection mechanism, respectively. It is found that the magnitudes of hole and electron trapping depend on both Fowler–Nordheim programming and erasing bias conditions. Sweeping gate voltage from strong accumulation to strong inversion, a gate current spike appears near the silicon midgap voltage in cycled devices and is attributed to the recombination between trapped holes in the tunneling oxide and tunneling electrons from the acceptor interface states above the intrinsic Fermi level