Design of a low power, double throughput cyclic combinational gate diffusion input based radix-4 MBW multiplier and accumulator unit for on-chip RISC processors of MEMS sensor

Modern microsystems based on sensor specific structures have robust on-chip digital signal processors to process the input signals. In order to improve the robustness of the system, on-chip processor circuitry has to be fabricated in limited areas with low latency and low power consumption. In this paper, a new technique for implementing low-power, high performance multiplier and accumulator (MAC) unit has been introduced for on-chip microelectromechanical systems applications. Based on cyclic combinational gate diffusion input technique, the proposed MAC unit is designed using Radix-4 modified Booth Wallace multiplier architecture and can operate up to 100 MBps of input data acquisition rate. Our proposed design is made of single threshold voltage transistors which employ low latency and reduced power consumption and less complexity in physical design. CAD tool based simulation at Generic 250 nm technology and comparison between proposed design with other available designs shows that the proposed design is better than many other designs for similar range of operation. The proposed design has an average power consumption of 98.8 mw and propagation delay of 6.8 ns at input bit rate 100 MBps for 16 bit operands. (paper)