Published 1990 | Version v1
Book

Monolithic CMOS front-end electronics with analog pipelining

  • 1. CERN, CH-1211 Geneva 23 (Switzerland)
  • 2. SSC Lab., Dallas (TX)
  • 3. Getec AS, Oslo (Norway)
  • 4. SI, Oslo (Norway)

Description

This paper reports on basic functional blocks designed and tested: Bipoltest, CSI, SAPE and PIPAD which are a front-end amplifier, a current sampling integrator, an analog pipeline and an analog/digital converter respectively. These functional blocks will eventually be combined in a single chip, and this processor will be the starting point for the HARP architecture. The signal amplifier peaking time for low capacitance detector elements is less than 15 ns. The sampling rate of the pipeline element in the 3 μm CMOS is measured to be 20 MHz with a dynamic range of ±1.2 pC of input charge which corresponds to 11 bits and the sampling rate in the 1.5 μm technology is over 60 MHz. The ADC operates at 1 MHz sampling rate with 12 mW for 11 bits precision

Additional details

Publishing Information

Publisher
IEEE Service Center.
Imprint Place
Piscataway, NJ (USA)
Imprint Title
IEEE nuclear science symposium conference record emdash 1990
Imprint Pagination
1636 p.
Journal Page Range
p. 543-552.

Conference

Title
1990 Institute of Electrical and Electronics Engineers (IEEE) nuclear science symposium.
Dates
22-27 Oct 1990.
Place
Arlington, VA (USA).

Optional Information

Secondary number(s)
CONF-9010220--.