Single-event upset sensitivity of latches in a 90nm dual and triple well CMOS technology

The sensitivity to Single Event Upset of latches designed in a 90nm dual and triple well CMOS technology has been measured irradiating a custom shift register with heavy ions. Latches designed with the NMOS transistors isolated from the substrate with a deep n-well (triple well) are only marginally less sensitive to SEUs, and only at high LET of the ions. The impact of lowering the voltage supply from 1.2 to 0.8V on the cross-section is limited to about 25%. Hits on the clock distribution network are observed and corrupt the data stored in multiple cells.