Negative gate bias stress effects on conduction and low frequency noise characteristics in p-type poly-Si thin-film transistors

The instability of p-channel low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) is investigated under negative gate bias stress (NBS) in this work. Firstly, a series of negative bias stress experiments is performed, the significant degradation behaviors in current–voltage characteristics are observed. As the stress voltage decreases from −25 V to −37 V, the threshold voltage and the sub-threshold swing each show a continuous shift, which is induced by gate oxide trapped charges or interface state. Furthermore, low frequency noise (LFN) values in poly-Si TFTs are measured before and after negative bias stress. The flat-band voltage spectral density is extracted, and the trap concentration located near the Si/SiO₂ interface is also calculated. Finally, the degradation mechanism is discussed based on the current–voltage and LFN results in poly-Si TFTs under NBS, finding out that Si–OH bonds may be broken and form Si* and negative charge OH⁻ under negative bias stress, which is demonstrated by the proposed negative charge generation model. (paper)