New ATLAS pixel Front-End chip for upgraded luminosity

Motivated by the upcoming upgrades of the ATLAS hybrid pixel detector at CERN (Insertable B-Layer project 2012 and super-LHC upgrade 2017), a new Front-End IC (FE-I4) is being developed in a 130 nm technology to face the tightened requirements of the upgraded pixel system. The design goals are to reduce the pixel size, reduce material, improve powering scheme, and cope with the much higher hit rate coming from both the increased luminosity and the potential smaller radius of the innermost pixel layer. New technology features are being used like higher integration density for digital circuits, better radiation tolerance and triple-well transistors. The digital readout has been completely redesigned to achieve low inefficiencies with increased hit rates and provide higher output data bandwidth. A description of the FE-I4 design is given, focusing on the digital and data processing blocks