The data acquisition system of the Belle II Pixel Detector

At the future Belle II experiment the DEPFET (DEPleted Field Effect Transistor) pixel detector will consist of about 8 million channels and is placed as the innermost detector. Because of its small distance to the interaction region and the high luminosity in Belle II, for a trigger rate of about 30 kHz with an estimated occupancy of about 3 % a data rate of about 22 GB/s is expected. Due to the high data rate, a data reduction factor higher than 30 is needed in order to stay inside the specifications of the event builder. The main hardware to reduce the data rate is a xTCA based Compute Node (CN) developed in cooperation between IHEP Beijing and University Giessen. Each node has as main component a Xilinx Virtex-5 FX70T FPGA and is equipped with 2 × 2 GB RAM , GBit Ethernet and 4 × 6.25 Gb/s optical links. An ATCA carrier board is able to hold up to four CN and supplies high bandwidth connections between the four CNs and to the ATCA backplane. To achieve the required data reduction on the CNs, regions of interest (ROI) are used. These regions are calculated in two independent systems by projecting tracks back to the pixel detector. One is the High Level Trigger (HLT) which uses data from the Silicon Vertex Detector (SVD), a silicon strip detector, and outer detectors. The other is the Data Concentrator (DATCON) which calculates ROIs based on SVD data only, in order to get low momentum tracks. With this information, only PXD data inside these ROIs will be forwarded to the event builder, while data outside of these regions will be discarded. First results of the test beam time in January 2014 at DESY with a Belle II vertex detector prototype and full DAQ chain will be presented