Data handling processor for Belle2 Vertex Detector

Motivated by the upcoming upgrade of the Belle experiment at the KEK e+e- collider in Japan, a new Vertex Detector is being design based on a DEPFET pixel matrix. A part of the new detector will be the Data Handling Processor (DHP) designed for handling the data produced by an analog readout chip, the DCD (drain current digitizer). The DHP will be directly placed on the DEPFET substrate. It is being developed in 90 nm CMOS technology. The goal of this design is to handle a high input data rate of about 24 Gb/s. Data reduction is possible thanks to triggering, on-chip correction and compression algorithms. The resulting data are sent to FPGA-based processing stages placed outside the inner detector using high speed serial links. A description of the DHP design is given, focusing on data processing and communication with other detector parts.