Electronics for BPM measurement at CSNS RCS

It introduces the design and implementation of the BPM electronics for CSNS RCS. The challenges of designing the BPM electronics are to acquire and process the signal with large dynamic range (5.8 mV∼32 V) and changing width (80 ns to 500 ns). The analog circuit described in this paper, which is constructed of single-stage amplifier and analog switch, can cover the input signal with large dynamic range. Besides, it is indispensable that the BPM electronics is able to calculate the position information. The algorithm developed in FPGA is able to make Bunch-by-Bunch position calculation and Closed Orbit position calculation in real time. In addition, many other functions useful for CSNS project have been implemented in this work, including the storage of the TBT position information for 30 s, reading and controlling via VME bus, on-line configuration of FPGA. Preliminary test results show that the resolution of Bunch-by-Bunch position is 0.9 mm when the input signal is 10 mV and the resolution of Closed Orbit position is 50 μm. (authors)