Low noise CMOS readout for CdZnTe detector arrays

A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 μm low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing function incorporated in the shaper provides low power and reduces chip area. The system is partitioned into a chip containing the charge amplifiers and a chip containing the semi-Gaussian pulse shaper and multiplexer. This architecture minimizes coupling from multiplexer switches as well as shaper output to the input of the charge sensitive preamplifiers