Electrical characteristics dependence on the channel fin aspect ratio of multi-fin field effect transistors

In this work we investigate the impact of the fin number and structure on device dc and dynamic behaviors of multi-fin field effect transistor (FET) circuits. Based on the same channel volume, multi-fin FETs with different fin aspect ratio (AR ≡ fin height/fin width) are explored using an experimentally validated three-dimensional device simulation. The multi-fin FinFET (AR = 2) has a better channel controllability than the tri-gate (AR = 1) and the quasi-planar (AR = 0.5) FETs. Besides, the 6T SRAM with triple-fin FinFETs provides the largest static noise margin because of the largest transconductance. Notably, though the FinFETs are with a large effective fin width and driving current, the larger gate capacitance may limit the intrinsic device gate delay. The transient characteristics of multi-fin inverters are further examined with different load capacitance (Cload). As Cload is increased, the impact of the device intrinsic gate capacitance on transient characteristcs is decreased and the delay time compared with that of single-fin inverters is smaller due to being dominated by the driving current of the transistor. Consequently, the multi-fin FinFET circuits exhibit a smallest delay time. The results of the study provide an insight into the dc and transient characteristics of multi-fin transistors and associated digital circuits