Published September 18, 2002 | Version v1
Report

A gigabit ethernet link source card

Description

A Link Source Card (LSC) has been developed which employs Gigabit Ethernet as the physical medium. The LSC is implemented as a mezzanine card compliant with the S-Link specifications, and is intended for use in development of the Region of Interest Building (ROIB) in the Level 2 Trigger of ATLAS. The LSC will be used to bring Region of Internet Fragments from Level 1 Trigger elements to the ROIB, and to transfer compiled Region of Interest Records to Supervisor Processors. The card uses the LSI 8101/8104 Media Access Controller (MAC) [1] and the Agilent HDMP-1636 Transceiver. An Altera 10K50A FPGA [2] is configured to provide several state machines which perform all the tasks on the card, such as formulating the Ethernet header, read/write registers in the MAC, etc. An on-card static RAM provides storage for 512K S-Link words, and a FIFO provides 4K buffering of input S-Link words. The LSC has been tested in a setup where it transfers data to a NIC in the PCI bus of a PC

Availability note (English)

Available from PURL: https://www.osti.gov/servlets/purl/801625-hL5WxH/native/

Additional details

Publishing Information

Imprint Pagination
3 p.
Report number
ANL-HEP-CP--02-77

Conference

Title
8. Workshop on Electronics for LHC Experiments
Dates
9-13 Sep 2002
Place
Colmar (France)

INIS

Country of Publication
United States
Country of Input or Organization
United States
INIS RN
34001752
Subject category
S43: PARTICLE ACCELERATORS; S99: GENERAL AND MISCELLANEOUS;
Resource subtype / Literary indicator
Conference, Non-conventional Literature
Descriptors DEI
ATLAS SUPERCONDUCTING LINAC; COMPUTER NETWORKS; DATA TRANSMISSION; DESIGN; OPERATION
Descriptors DEC
ACCELERATORS; COMMUNICATIONS; HEAVY ION ACCELERATORS; HILACS; LINEAR ACCELERATORS

Optional Information

Contract/Grant/Project number
W-31-109-ENG-38
Funding organization
US Department of Energy (United States)