Published November 12, 2010
| Version v1
Journal article
Flip-chip fabrication of nanoscale co-planar embedded electrodes with controlled exposed areas
- 1. School of Electronic and Electrical Engineering, University of Leeds, Leeds LS2 9JT (United Kingdom)
Description
We discuss the fabrication of closely spaced nanoscale embedded co-planar electrodes with concealed contact wires, using a GaAs-based flip-chip technology. The co-planarity of the electrodes with the substrate and the low roughness of the exposed surface are achieved by templating the deposition of both the dielectric and electrode metal onto a smooth GaAs substrate. The resulting electrodes, with sizes of around 300 nm and separations as low as 25 nm, have RMS roughnesses of less than 0.2 nm and a co-planarity of around 1 nm.
Availability note (English)
Available from http://dx.doi.org/10.1088/0957-4484/21/45/455301Additional details
Identifiers
- DOI
- 10.1088/0957-4484/21/45/455301;
- PII
- S0957-4484(10)58055-3;
Publishing Information
- Journal Title
- Nanotechnology (Print)
- Journal Volume
- 21
- Journal Issue
- 45
- Journal Page Range
- [6 p.]
- ISSN
- 0957-4484
INIS
- Country of Publication
- United Kingdom
- Country of Input or Organization
- International Atomic Energy Agency (IAEA)
- INIS RN
- 43024730
- Subject category
- S77: NANOSCIENCE AND NANOTECHNOLOGY;
- Descriptors DEI
- DEPOSITION; ELECTRODES; FABRICATION; GALLIUM ARSENIDES; METALS; NANOSTRUCTURES; ROUGHNESS; SUBSTRATES; SURFACES
- Descriptors DEC
- ARSENIC COMPOUNDS; ARSENIDES; ELEMENTS; GALLIUM COMPOUNDS; PNICTIDES; SURFACE PROPERTIES