Published December 8, 2004 | Version v1
Journal article

Examination of Critical Length Effect in Copper Interconnects With Oxide and Low-k Dielectrics

  • 1. CMOS Platform Device Development, Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, TX 78721 (United States)
  • 2. Advanced Products Research and Development Laboratory, Technology Solutions Organization, Freescale Semiconductor, Inc., Austin, TX 78721 (United States)

Description

As technology moves toward faster microelectronic devices with smaller feature sizes, copper is replacing aluminum-copper alloy and low-k dielectric is replacing oxide as the materials of choice for advanced interconnect integrations. Copper not only brings to the table the advantage of lower resistivity, but also exhibits better electromigration performance when compared to Al(Cu). Low-k dielectric materials are advantageous because they reduce power consumption and improve signal delay. Due to these advantages, the industry trend is moving towards integrating copper and low-k dielectric for high performance interconnects. The purpose of this study is to evaluate the critical length effect in single-inlaid copper interconnects and determine the critical product (jl)c, for a variety of integrations, examining the effect of ILD (oxide vs. low-k), geometry, and stress temperature

Additional details

Identifiers

Publishing Information

Journal Title
AIP Conference Proceedings
Journal Volume
741
Journal Issue
1
Journal Page Range
p. 165-172
ISSN
0094-243X
CODEN
APCPCS

Conference

Title
7. international workshop on stress-induced phenomena in metallization
Dates
14-16 Jun 2004
Place
Austin, TX (United States)

INIS

Optional Information

Notes
(c) 2004 American Institute of Physics