Front-end electronics for DEPFET pixel detectors at SuperBelle (BELLE II)

This article gives an overview of the front-end electronics development for the DEPFET pixel vertex detector at the Super KEK-B experiment (BELLE II). The planned upgrade of the KEK-B factory will lead to a peak luminosity of 8x1035cm-2s-1. This increase in luminosity (x50 compared to the existing experiment) will make high demands on the performance of the vertex detector. The proposed two layer vertex detector consists of 'all-silicon' modules: the read-out and control ASICs will be bump bonded on the rigid edges of the DEPFET substrate whereas in the region of the active pixel matrix the substrate will be thinned down to 50μm. The front-end electronics is subdivided in three different ASIC types: one chip will provide up to 20 V output swing for the control voltages of the DEPFET matrix (SWITCHER), the current signals are being digitized by a multichannel ADC chip (DCD) and the processing of the digital data and module control functionality is implemented in a data handling chip (DHP). An overview of the module concept and the status of the developments including results of current prototype chips will be given.