A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background

A 14-bit 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) is presented. In addition to elaborate matching of the sampling network in the first stage, a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18-μm CMOS technology, the presented ADC occupies a chip area of 12 mm², and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-dB signal-to-noise and distortion ratio (SNDR), an 85.4-dB spurious-free dynamic range (SFDR), a maximum differential nonlinearity (DNL) of 0.22 LSB and a maximum integral nonlinearity (INL) of 1.4 LSB. (paper)