Results of 65 nm pixel readout chip demonstrator array

Complex and challenging instrumentation projects (LHC upgrades, HL LHC, new Detector concepts) will require the adoption of ever more empowering and complex IC technologies. We clearly see that by moving only two nodes from the current 130 nm CMOS to 65 nm, substantial processing power could be embedded in the front-end system. We have designed and fabricated a prototype pixel readout chip to explore 65 nm CMOS as a potential integrated circuit technology for future particle physics applications. Not only the reported functional test results are very encouraging, but we also found that the process is fundamentally tolerant to radiation doses higher than 600 Mrad.