Highly efficient high-performance sense amplifier design in nanoscale CMOS technologies

Nowadays the tendency of design of integrated circuits goes in the power and area reduction way. Power reduction requires usage of low-power design methodologies. The latter, in turn, requires decreasing the supply voltage values. This impacts on the stability of the sensitive parts of analog and mixed-signal integrated circuits. Sense amplifiers are widely used in modern integrated circuits. They play a key role in memory circuits and act as the most complex parts from the standpoint of designing. A stability improvement method of those circuits in modern nanoscale integrated circuits is proposed in this paper. A new sense amplifier architecture has been proposed in which the current - controlled bandwidth has been provided highly efficient power consumption results. Besides the current-controlled architecture has ensured the minimization of comparator offset dependency on the power supply value